This invention relates to Field Effect Transistor (FET) Static Random Access Memory (SRAM) devices, and more particularly to finFET structures and methods of manufacture of finFET SRAM devices.
It is possible to change the length of finFET devices to reduce the on-current of a finFET device as exemplified in Yang et al., “Fully Working 1.25 mm2 6T-SRAM cell with 45 nm gate length Triple Gate Transistors,” IEDM Tech. Dig., 2003, pp. 23-26. However, there is a problem in that devices with longer channel lengths not only require a larger portion of the silicon substrate area, but variables are introduced in terms of the variability of the physical dimensions of the gate lengths due to the complexities of optical proximity correction. In addition, different gate lengths give different short channel effect characteristics, which can cause threshold voltage mismatching or ratio variation induced by Vdd variation.
Another approach by Aller et al., in U.S. Patent Application Publication No. 2004/0222477 which issued as U.S. Pat. No. 6,909,147 discloses a finFET device provided with a first semiconductor fin and a second semiconductor fin with different heights. Adjustments of the ratio of the height of the first semiconductor fin to that of the second semiconductor fin are used to tune the performance of the transistor. However, the use of a thermal oxidation process to reduce the height of the fin requires that a hardmask be used in this process. Many processing steps are necessary such as deposition of a hardmask material, application and lithographic patterning of a photoresist, a transfer of a lithographic pattern into the hardmask, and thermal oxidation. The oxidation raises the surface level due to volume expansion caused by the oxidation, which causes lithographic variations or CD printing variations.